LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY one_double IS
    PORT (
        in_c  : IN  STD_LOGIC;
        out_c : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END one_double;

ARCHITECTURE behav OF one_double IS
BEGIN
    PROCESS(in_c)
    BEGIN
          
			out_c<= (others => '0');  -- 无符号扩展
			out_c(0) <= in_c;  
    END PROCESS;
END behav;